Stereo to Mono output mixing - Common base amplifier
This is an interesting exercise in my recollection of Transistor parameters and basic circuit design. The approach can be applied to any circuit design in that we need to understand the surrounding parameters and what we need the function to do.
Here is the challenge. I was designing a piece of circuitry for a project and didn't look at the interface between an audio circuit and the circuit which processes this information.
Basically the output of the audio circuit is 100mV ( 0.1 V) and I need to get this amplified to 3.3V or at least 2.8V. The audio is stereo signal ( its split into two ) so we need to combine the two channel into one to make a mono channel and then boost.
The specification
Lets look at what I know about the 'red' block. The output signal needs to reach a Vih of >=1.8V for logic detection.
Gain ( amplification) is 1.8V / 0.1 = 18. The gain or Beta ( HFE) is 18+
I also need to know the (Zo) output impedance of the audio generator and the (Zin) input impedance of the processing unit as we want o match these as closely as possible for the frequency range.
As for the frequency range I need a flat gain response upto around 60kHz at a 3dB cutoff and a gradual filtering of any frequencies above this ; basically a low pass filter with a cutoff at 60kHz.
Z out (Zo) of the Audio generator is stating is no less than 32R. So we can play with 100R to start with.
Zin is the input to the processor and is a max of 50K; which is fairly high impedance.
Here is the circuit. The values at present have been played with so its not the final circuit but the start.
The circuit is based around the 2N2222A transistor which is a fairly good standard transistor, BC109, BC108 are all very similar and its a general purpose transistor which helps cost.
The mixer is based around a common base transistor configuration. You can see that the base is biased with R4 and R3 to get the set-point. C1 is our filter of the R3/R4 potential divider. Our two stereo signals come in C3 and C2 directly into the emitter of the transistor. The combined mono output is provided through C4 and decoupled by this capacitor when connecting to the processing unit.
VCC = 3.3V
Rin = 100R
AV ( voltage gain ) = Vc/Ve -> IcRc / (Ie(r'e//RE)) and approx IeRc/ (Ie(r'e//RE)).
If RE >> r'e then Av = RC/ r'e ; and Rc = RC//RL
Looking at VB it is calculated using R2/(R1+R2) * VCC
In reality the gain is approx the ratio of RC to RE.
Pumping values into the circuit simulation.
The simulation result is
The poor low frequency response is due to the capacitor values chosen and changing these to 100uF is a good choice but I don't have the PCB space.
R5 Input impedance has a marked impact on the gain and so may be an issue. The Voltage level is about 2.1 V which is above the required ViH of 1.8V.
However the calculations between theoretical gain and simulated are an order of magnitude out. My calculations are AV = 5 and the simulation values give me a gain of 20.
Using smaller capacitance means that my audio will lose some of the lower end frequencies and my signals cannot go lower than 158Hz. My upper roll-off for the circuit was around the 1Mhz. So I added a small capacitance to the transistor output to reduce the roll-off.
The addition of the 47pF allows the cut-off to sit at 200kHz and protect the signal from potential clock noise from the digital circuits.
The diagram above also shows the frequency response is flat in the region I need and the phase change is relatively flat also. If I were to decrease increase the 47pF to 10pf or 22pF, I get less phase change at the expense of my upper filter cut-off frequency. But at these capacitance values just the board layout and impedance of the connecting circuit will have a bigger impact; so not worth chasing until we need to.
Next step is to build and test the circuit.
Using the predicted simulation values for components is very disappointing. The upper cut-off frequency is 1.2kHz and markedly down on what was expected. This circuit has a limited phase change and a great frequency range as the miller effect doesn't come into play. The circuit is used for first stage antenna coupling followed by a common collector or common emitter circuit so widely used and trusted. However the biasing is critical for its operation and this will become evident.
I found a great site with a Common-base calculator which will help me understand the challenges.
The key specifications for me are matched 32ohm input or slightly more. High output impedance. limited phase change in the frequency range of interest and a 3dB cut-off around 100kHz or more. Operation at 3.3V - 2.8V and a signal output that gets over a ViH of 1.8V to 0V.
One thing of interest is that HFE is lower at these voltages approx 35-50 rather than 200 ish. The circuit has near unity current gain. So if I need current to drive something I better make sure that the current through R1 is sufficient.
I also found this great site to play around with values http://www.vk2zay.net/calculators/ this has helped me explore the factors affecting the design.
Simple breadboard layout:
So with the original values this is what I saw on the scope: First the PC generated output signal as a sine wave 100mV pk to pk.
This is the square wave output from PC; and its not great.
This is the output at 1kHz and you can see the low pass effect of the circuit rounding off the square wave. The amplitude is about a volt.
Clearly the design is not working as expected.
Next is to recalculate based on the values generated by the calculator in the link above.
Here is the final circuit and the original simulator isn't working so its a case of trusting the on-line calculator.
So this is starting to look like a good swing of voltage. The square-wave seems nicely formed. But when I pump through a sine wave there is notable clipping which means my bias point is off> I also reduced RE to 193R = 330R //1500R for matching. While I am not spot on with values this will work. The only thing is that I cannot yet achieve is the high cut-off frequency and I have only managed to push this to approx 2400Hz.
This is not a great Sine wave output due to clipping. This waveform is interesting as this may be the effects of R'e on the emitter.
I have now moved to the Eagle NGspice to model the circuit:
With a few simulations. I get to what seems an optimal solution and values that are pretty close.
The addition of the 22pF capacitor gives some roll off around the 220kHz region. The centre of what is essentially a band pass filter is around the 50kHz frequency.
The bias is not quite correct as there is some clipping of negative half of the waveform when a sinusoid is input. The lower bound is around the frequency of 1600Hz or 1.8KHz and that roughly coincides with the Vbe of the transistor.
This configuration is known for high voltage gain, unity current gain, low input impedance and high output impedance and does not suffer from the Miller effect. So you essentially have a building block for a band pass filter which can be connected to microphones or antenna; so it remains a useful circuit for HF,
Some caution is needed here, as the NPN transistor model is near ideal or generic and we need to do the simulation with a 2N2222A transistor - Another blog post.
Finally I want to find the optimum AC coupling capacitor that I need for the circuit.
As the input capacitor and Zin is effectively a high pass filter the equation is:
For a capacitor value of 100nF and RE of 1.5K , fc theoretical is 1.1Khz at a VBe of 0.6V.
The simulation is pretty close:
If we increase AC decoupling to 1uF we shift the lower frequency response by a decade so roughly 110Hz.
Conclusion
The Common base amplifier is quite a challenge to setup. However its use for low to high impedance matching is extremely useful. I like the band pass effects here. The operation at 3.3V has been a challenge and I am not sure i have fully explored some of the 2N2222A characteristics including the r'e effects in the output circuit.
The ratio of R5 to R1 is critical. So once a load is added R1 will need a tweak to adjust for the expected gain which is roughly 30X or 29.5 dB.
References and Acknowledgements
Many thanks to the following Youtubers for a nice visual explanation.
A special thank you to DonationCoder.com for what is simply the best screen capture tool on the market and is free to download; although a donation is always a handy acknowledgement of the hazard work going into the software development.
Finally Eagle, which uses NGSpice, and while I tried others, I just came back to its ease of use and great modelling output.
Next step is the breadboard build and coupling up.
Comments
Post a Comment